Advances in the miniaturization of semiconductor devices lead to better-performance and increased storage capacity for end-users. Many process steps are involved in the manufacturing of the semiconductor device. One step is the doping of semiconductor substrate to form source/drain junctions. Ion-implantation is used to modify the electrical characteristics of the semiconductor substrate by the implantation of specific dopant impurities into the semiconductor wafer surface. The dopants that are commonly used are Boron, Arsenic and Phosphorus; other dopants can be used as well and are always being investigated. With the use of ion-implantation a post annealing treatment is desired to complete the activation process as well as repair any associated damage to the implanted region. Post anneal treatments can differ based on the implant dosage (the amount of atoms implanted in the surface) and the implant energy (the depth of atoms into the wafer surface). Implants that are greater than approximately ˜5 keV and dosages greater than approximately 4E15 atoms/cm3 form an amorphous layer that is re-grown using the post anneal process and are subject to end of range (EOR) defects, or un-repaired damage. Implants less than approximately 5 keV do not form an amorphous layer and are considered Ultra Shallow Junction (USJ) implants, which also utilize a post anneal process to electrically activate the dopants. Unfortunately, the post-implantation anneal becomes more challenging due to the limitations of dopant diffusion, the damage recovery percentage, and the thermal budget for the next generation of semiconductor devices. The development of post annealing processing equipment able to meet operational requirements has been difficult.
Annealing techniques have included furnace processing, Rapid Thermal Processing (RTP), Rapid Thermal Annealing (RTA), which includes Flash Annealing, and various versions of Laser Annealing. Unfortunately, each of these methods are associated with certain problems and disadvantages. For example, Rapid Thermal Processing is a high-temperature process, i.e., 800 degrees C. to 1100 degrees C., which can cause degradation to the performance of the semiconductor material, as well as an undesired diffusion of the dopant into the surrounding material. Similarly, Laser Annealing methods are hampered by process integration issues mainly due to the “pattern effects” of the layers. For example in the laser anneal process, a laser is used with a spot size diameter of approximately 3 mm. Although, the area within the spot size is activated, it is much smaller than the total area needed to be activated on the wafer surface. So the laser is used many times and moved each time to cover the entire implanted area. As a result, there is overlapping and/or missed areas forming a “pattern”. In terms of manufacturing requirements, laser annealing is typically a slower process of approximately one wafer per hour, whereby approximately twenty wafers per hour is commercially desired.
There are also annealing techniques using microwave energy, see, e.g., U.S. Pat. No. 4,303,455. In this context, the term “microwave” is often used rather loosely to refer to electromagnetic radiation in the millimeter, microwave, and radio-frequency spectrums. Microwave annealing more evenly heats the entire volume from the inside outward (as opposed to from the surface inward) of the semiconductor material. The volumetric absorption of microwave heating in dielectric lossy materials has been used in a number of different applications, including in the thermal processing of ceramic materials; however, the application to semiconductor materials is rather new and limited. Experiments using magnetron and gyrotron sources in combination with multi-mode processing chambers have been attempted. Heating rates of approximately 100 degrees C./sec and processing temperatures of approximately 1000 degrees C. over a few seconds were achieved, yet demonstrated no improvement over the RTP techniques. Largely due to the use of fast ramp rates and high microwave power fields, the temperature of the wafer exceeded 800 degrees C., resulting in the thermal radiation within the wafer becoming dominate, thereby minimizing any advantage associated with microwave heating.
In methods currently used, heating times must be severely minimized to limit the increase of the thermal budget (the total amount of thermal energy transferred to the wafer during the given elevated temperature operation) because higher temperatures are used in the annealing process.
Due to these and other problems and disadvantages in the prior art, a need exists for an improved system for and method of annealing semiconductor materials.